Computing array based on 1t1r device, operation circuits and operating methods thereof

ABSTRACT

The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

BACKGROUND OF THE INVENTION Technical Field

The present invention belongs to the field of microelectronic devices, and more particularly relates to a computing array based on 1T1R device, operation circuits and operating methods thereof.

Description of the Related Art

In the era of big data, the Moore's Law for integrated circuits, which improve the computational performance through the size reduction of nano-transistor logic devices, has been difficult to continue. The bottleneck problem of storage and computation separation in the traditional von Neumann computing architecture is highlighted, and the existing architecture and hardware cannot meet the demand for superior computing power in explosive growth of information.

Resistive Random Access Memory (RRAM), which has the characteristics such as low power consumption, high speed, high integration as well as information storage and calculation functions, can break through the limit of Moore's Law in the development of existing electronic devices, and thus is widely used in improving the speed of computer data processing. In the existing industrial integration technology, RRAM is mainly applied in the 1T1R device structure.

Chinese Patent No. 2014203325960 proposed a non-volatile Boolean logic operation circuit and an operating method thereof, which realizes a complete set of non-volatile Boolean logic operations through a back-to-back RRAM structure, but cannot realize circuit cascading, circuit integration and more complex computing functions.

SUMMARY OF THE INVENTION

In view of the above-described defects or improvement requirements in the art, the present invention provides a computing array based on 1T1R device, operation circuits and operating methods thereof, which aim to achieve a complete set of non-volatile Boolean logic operations, and to achieve more complex computing functions, while improving the compatibility of the computing circuits and simplifying the operation methods.

In order to achieve the above objective, according to a first aspect of the present invention, there is provided a computing array based on 1T1R device, which comprises: one or more 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays.

The 1T1R array includes 1T1R devices arranged in an array, word lines WL, bit lines BL and source lines SL; resistance states of the 1T1R devices include: High Resistance H and Low Resistance L; the 1T1R devices realize storage and processing of information through different resistance states; and the 1T1R devices in the same row are connected to the same bit line, the 1T1R devices in the same column are connected to the same bit line and source line, and through applying different signals to the word lines WL, the bit lines BL and the source lines SL, different operations are achieved and operation results are stored.

The 1T1R device includes a transistor and a resistive element; the transistor includes a substrate, a source, a drain, an insulating layer and a gate, in which the source is connected to the source line SL, and the gate is connected to the word line WL; the resistive element includes two end electrodes, one of which is connected to the bit line BL and the other of which is connected to the drain of the transistor; and the resistive element has a stacked structure with a nonvolatile resistance transition characteristic.

The resistance state of the 1T1R device can be reversibly transformed under the stimulation of an applied signal, namely, with the stimulation of an applied signal, the resistance state of the 1T1R device can be transformed from High Resistance to Low Resistance, and with the stimulation of another applied signal, the resistance state of the 1T1R device can be transformed from Low Resistance to High Resistance. By using the two resistance states of the 1T1R device, storage and processing of information can be achieved.

In a first embodiment of the first aspect of the present invention, the resistive element of the 1T1R device is RRAM; RRAM includes: an upper electrode, a functional layer and a lower electrode; the upper electrode is connected to the bit line BL, and the lower electrode is connected to the drain of the transistor.

The peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit, wherein:

The state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result.

An input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to a word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array.

An input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to a bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array.

An input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to a source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array.

The word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array.

An input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem.

A first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array.

An input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.

The data input/output terminal Data, the address input terminal Address and the clock signal input terminal CLK of the state controller respectively serve as a data input/output terminal, an address input terminal and a clock signal input terminal of the computing array.

In the computing array based on 1T1R device, applied voltage pulses are used as input signals to perform logic operation, and the result of the logic operation is characterized by the final resistance state of the 1T1R device; the result of the logic operation can be non-volatilely stored in the resistance state of the device, the resistance state can be read by a read signal of a small current (generally at the nanoampere level) or a small voltage (generally 0.2V or less), and the resistance signal can be erased by applying a voltage pulse with a certain amplitude and pulse width.

In the computing array based on 1T1R device, Boolean logic operations are achieved in the 1T1R devices by applying different voltage pulse signals to the word lines, source lines and bit lines of the 1T1R array. The initial resistance state of the 1T1R device is defined as a logic signal I, in which I=0 when the initial resistance state of the 1T1R device is High Resistance, and I=1 when the initial resistance state of the 1T1R device is Low Resistance; the word line level voltage is defined as a logic signal V_(WL), in which V_(WL)=0 when a zero-level pulse is applied to the word line, and V_(WL)=1 when a forward voltage pulse is applied to the word line; the bit line level voltage is defined as a logic signal V_(BL), in which V_(BL)=0 when a zero-level pulse is applied to the bit line, and V_(BL)=1 when a forward voltage pulse is applied to the bit line; the source line level voltage is defined as a logic signal V_(SL), in which V_(SL)=0 when a zero-level pulse is applied to the source line, and V_(SL)=1 when a forward voltage pulse is applied to the source line; the result of the logical operation in the 1T1R device is non-volatilely stored in the 1T1R device, and when information stored in the 1T1R device is read, the resistance state of the 1T1R device is defined as a logic signal R, in which R=0 when the resistance state of the 1T1R device is High Resistance, and R=1 when the resistance state of the 1T1R device is Low Resistance; and a logical relationship between the logic signal I, the logic signal V_(WL), the logic signal V_(BL), the logic signal V_(SL), and the logic signal R is:

R=I· V _(WL) +I·V _(WL) ·V _(BL) +I·V _(WL)· V _(BL) · V _(SL) +Ī·V _(WL) ·V _(BL)· V _(ST)

In the computing array based on 1T1R device, Boolean logic operation are implemented in a single 1T1R device, and specifically, the operating method includes the following steps.

(1) Initializing the 1T1R device to obtain a logic signal I.

(2) Respectively applying a voltage pulse signal to a word line, a source line and a bit line to obtain a logic signal V_(WL), a logic signal V_(SL) and a logic signal V_(BL).

(3) Reading a result of the logical operation, that is, a logic signal R.

By controlling values of the logic signals I, V_(WL), V_(BL) and V_(SL), the following 16 Boolean logic operations can be implemented:

implementation of logic 0: I=0, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of logic 1: I=1, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=0 and V_(SL)=q;

implementation of p logic: I=q, V_(WL)=0, V_(BL)=0 and V_(SL)=p;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of q logic: I=q, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=p, V_(WL)=1, V_(BL)=p and V_(SL)=0;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=0 and V_(SL)=q;

implementation of p·q logic: I=0, V_(WL)=p, V_(BL)=q and V_(SL)=0;

implementation of p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p+q logic: I=1, V_(WL)=1, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p·q logic: I=q, V_(WL)=1, V_(BL)=0 and V_(SL)=p;

implementation of p·q logic: I=p, V_(WL)=1, V_(BL)=0 and V_(SL)=q;

implementation of p·q+p·q logic: I=p, V_(WL)=q, V_(BL)=p and V_(SL)=p; and

implementation of p·q+p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=q.

Further, by inputting a logic signal V_(WL)=1 via the word line, a logic signal V_(BL)=V_(read) via the bit line and a logic signal V_(SL)=0 via the source line, the logic signal stored in the 1T1R device can be read, in which V_(read) is a voltage pulse signal applied when the resistance state of the 1T1R device is read.

In the present invention, symbols similar to I, V_(WL), V_(BL) and V_(SL) are used to denote logical signals with the same concept, and signals corresponding to different 1T1R devices are distinguished only by different subscripts

According to a second aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a 1-bit full adder, in which a sum s₀ and a high-order carry c₁ are calculated according to a logic signal a, a logic signal b and a low-order carry c₀ that are input; the operation circuit comprises: a 1T1R array A₁, a 1T1R array A₂ and a 1T1R array A₃; the 1T1R array A₁ includes a 1T1R device R_(b) for calculating and storing intermediate data s₀*, a word line signal corresponding to R_(b) is V_(WLb), a bit line signal corresponding to R_(b) is V_(BLb) and a source line signal corresponding to R_(b) is V_(SLb); the 1T1R array A₂ includes a 1T1R device R_(c) for calculating and storing the high-order carry c₁, a word line signal corresponding to R_(c) is Y_(WLc), a bit line signal corresponding to R_(c) is V_(BLc) and a source line signal corresponding to R_(c) is V_(SLc); the 1T1R array A₃ includes a 1T1R device R_(s) for calculating and storing the sum s₀, a word line signal corresponding to R_(s) is V_(WLs), a bit line signal corresponding to R_(s) is V_(BLs) and a source line signal corresponding to R_(s) is V_(SLs); and the intermediate data s₀* calculated by the 1T1R array A₁ and the high-order carry c₁ calculated by the 1T1R array A₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array A₃ through the data transmission circuit.

In conjunction with the second aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:

(S1-1) Inputting logic signals V_(WLc)=1, V_(BLc)=c₀ and V_(SLc)=c₀ to write the input logic signal c₀ into R_(c) of the 1T1R array A₂; inputting logic signals V_(WLb)=1, V_(BLb)=a₀ and V_(SLb)=a₀ to write the input logic signal a₀ into R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=1, V_(BLs)=a₀ and V_(SLs)=a₀ to write the input logic signal a₀ into R_(s) of the 1T1R array A₃.

(S1-2) Inputting logic signals V_(WLc)=1, V_(BLc)=a₀ and V_(SLc)=b₀ to calculate a high-order carry c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(c) of the 1T1R array A₂; inputting logic signals V_(WLb)=b₀, V_(BLb)=a₀ and V_(SLb)=a₀ to calculate an intermediate result s₀*=a₀⊕b₀ and store s₀* in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=b₀, V_(BLs)=a₀ and V_(SLs)=a₀ to calculate an intermediate result s₀* and store s₀* in R_(s) of the 1T1R array A₃.

(S1-3) Reading the logic signal c₁ stored in R_(c) of the 1T1R array A₂; reading the logic signal s₀ stored in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=c₀, V_(BLs)=s₀* and V_(SLs)=s₀* to calculate a sum s₀=a₀⊕b₀⊕c₀ and store s₀ in R_(s) of the 1T1R array A₃.

(S1-4) reading the logic signal s₀ stored in R_(s) of the 1T1R array A₃.

According to a third aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a multi-bit step-by-step carry adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(0˜n−1) and carry information c₀, and n represents the number of bits of the operation data, the operation circuit comprises: a 1T1R array D₁, a 1T1R array D₂ and a 1T1R array D₃; the 1T1R array D₁ includes n 1T1R devices R_(0b)˜R_((n−1)b) for calculating and storing intermediate results s_(0˜n−1)*, word line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(WL0b)˜V_(WL(n−1)b), bit line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(BL0b)˜V_(BL(n−1)b), and source line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(SL0b)˜V_(SL(n−1)b); the 1T1R array D₁ is used for data backup; the 1T1R array D₂ includes a 1T1R device R_(n) for calculating and storing carry data c_(i) (i is an integer from 0 to n), a word line control signal corresponding to R_(n) is V_(WLn), a bit line control signal corresponding to R_(n) is V_(BLn) and a source line control signal corresponding to R_(n) is V_(SLn); the 1T1R array D₃ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the intermediate data s_(0˜n−1)* calculated by the 1T1R array D₁ and the carry information c_(i) calculated by the 1T1R array D₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array D₃ through the data transmission circuit.

In conjunction with the third aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:

(S2-1) Inputting logic signals V_(WL0˜(n−1)), V_(BL0˜(n−1))=a_(0˜n) and V_(SL0˜(n−1))=a_(0˜n) , to write the input data a_(0˜n−1) into R_(0˜n−1) of the 1T1R array D₃; inputting logic signals V_(WLn)=1, V_(BLn)=c₀ and V_(SLn)=c₀ to write the carry information c₀ into R_(n) of the 1T1R array D₂, a word line input signal, a bit line input signal and a source line input signal of the 1T1R array D₁ being the same as that of the 1T1R array D₃.

(S2-2) Inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to calculate intermediate results s_(0˜n−1)=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* in R_(0˜n−1) of the 1T1R array D₃; inputting logic signals V_(WL0b˜(n−1)b)=b_(0˜n−1), V_(BL0b˜(n−1)b)=a_(0˜n−1) and V_(SL0b˜(n−1)b)=a_(0˜n−1) to calculate intermediate results s_(0˜n−1)* and store s_(0˜n−1)* in R_(0b˜(n−1)b), of the 1T1R array D₁; inputting logic signals V_(WLn)=1, V_(BLn)=a₀ and V_(SLn)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(n) of the 1T1R array D₂.

(S2-3) Reading s₀* from R_(0b) of the 1T1R array D₁, and reading s₁* from R_(1b) of the 1T1R array D1; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜n−1)=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜n−1)=0, V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜n−1)=0 to calculate s₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array D₃ and s₁ in R₁ of the 1T1R array D₃.

(S2-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2.

(S2-5) Inputting logic signals V_(WLn)=1, V_(BLn)=a_(i−1) and V_(SLn)=b_(i−1) to calculate c_(i)=a_(i−1)·b_(i−1)+a_(i−1)·c_(i−1)+c_(i−1)·b_(i−1) and store c_(i) in R_(n) of the 1T1R array D₂.

(S2-6) Reading s_(i)* from R_(ib) of the 1T1R array D₁; inputting logic signals V_(WL0˜(i−1))=0, V_(WL2)=c_(i), V_(WL(i+1)˜(n−1))=0, V_(BL0˜(i−1))=0, V_(BL2)=s₁*, V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0, V_(SL2)=s_(i)* and V_(SL(i+1)˜(n−1))=0 to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i) and store s_(i) in R_(i) of the 1T1R array D₃.

(S2-7) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S2-5); otherwise, proceeding to step (S2-8).

(S2-8) Inputting logic signals V_(WLn)=1, V_(BLn)=a_(n−2) and V_(SLn)=b_(n−2) to calculate c_(n−1)=a_(n−2)·b_(n−2)+a_(n−2)·c_(n−2)+c_(n−2)·b_(n−2) and store c_(n−1) in R_(n) of the 1T1R array D₂.

(S2-9) Reading s_((n−1))* from R_((n−1)b) of the 1T1R array D₁; inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−2))=0, V_(BL(n−1))=s_(n−1)*, V_(SL0˜(n−2))=0 and V_(SL(n−1))=s_(n−1)* to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array D₃.

(S2-10) inputting logic signals V_(WLn)=1, V_(BLn)=a_(n−1) and V_(SLn)=b_(n−1) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(n) of the 1T1R array D₂.

According to a fourth aspect of the present invention, there is provided an operation circuit based on the computing array for implementing an optimized multi-bit step-by-step carry adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(0˜n−1) and carry information c₀, and n represents the number of bits of the operation data; the operation circuit comprises: a 1T1R array E₁, a 1T1R array E₂ and a 1T1R array E₃; the 1T1R array E₁ includes n 1T1R devices R_(0b)˜R_((n−1)b) for calculating and storing data s_(0˜n−1)*, word line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(WL0b)˜V_(WL(n−1)b), bit line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(BL0b)˜V_(BL(n−1)b), and source line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(SL0b)˜V_(SL(n−1)b); the 1T1R array E₁ is used for data backup; the 1T1R array E₂ includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculating and storing carry data c_(i) (i is an integer from 0 to n), word line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(WL0c)˜V_(WLnc), bit line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), and source line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array E₃ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the intermediate data s_(0˜n−1)* calculated by the 1T1R array E₁ and the carry information c_(i) calculated by the 1T1R array E₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array E₃ through the data transmission circuit.

In conjunction with the fourth aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:

(S3-1) Inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to write the input operational data a_(0˜n−1) into R_(0˜n−1) of the 1T1R array E₃; inputting logic signals V_(WL0b˜(n−1)b)=1, V_(BL0b˜(n−1)b)=a_(0˜n−1) and V_(SL0b˜(n−1)b)=a_(0˜n−1) to write the input operational data a_(0˜n−1) into R_(0b˜(n−1)b) of the 1T1R array E₁; inputting logic signals V_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to write the carry information c₀ into R_(0c˜nc) of the 1T1R array E₂.

(S3-2) Inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to calculate intermediate results s_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* in R_(0˜n−1) of the 1T1R array E₃; inputting logic signals V_(WL0b˜(n−1)b)=b_(0˜n−1), V_(BL0b˜(n−1)b)=a_(0˜n−1) and V_(SL0b˜(n−1)b)=a_(n) to calculate intermediate results s_(0˜n−1)* and store s_(n˜n−1)* in R_(0b˜(n−1)b) of the 1T1R array E₁; inputting logic signals V_(WL0c)=0, V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜8c)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array E₂.

(S3-3) Reading s₀* from R_(0b) of the 1T1R array E₁, and reading s₁* from R_(1b) of the 1T1R array E1; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜(n−1))=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜(n−1))=0, V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜(n−1))=0 to calculate s₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array E₃ and s₁ in R₁ of the 1T1R array E₃; inputting logic signals V_(WL0c˜1c)=0, V_(WL2˜nc)=1, V_(BL0˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜nc) of the 1T1R array E₂.

(S3-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2.

(S3-5) Reading s_(i)* from R_(ib) of the 1T1R array E₁; inputting logic signals V_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0, V_(BL0˜(i−1))=0, V_(BLi)=s_(i)*, V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0, V_(SLi)=s_(i)* and V_(SL(i+1)˜(n−1))=0 to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i), and store s_(i) in R_(i) of the 1T1R array E₃; inputting logic signals V_(WL0c˜ic)=0, V_(WL(i+1)c˜nc)=1, V_(BL0c˜nc)=a_(i) and V_(SL0c˜nc)=b_(i) to calculate c_(i+i)=a_(i)·b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) in R_((i+1)c˜nc) of the 1T1R array E₂.

(S3-6) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S3-5); otherwise, proceeding to a step (S3-7).

(3-7) Reading s_(n−1)* from R_((n−1)b) the 1T1R array E₁; inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−2))=0, V_(BL(n−1))=s_(n−1) *, V_(SL0˜(n−2))=0 and V_(SL(n−1))=s_(n−1)* to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array E₃; and inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1, Y_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−i) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(nc) of the 1T1R array E₂.

According to a fifth aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a 2-bit data selector, in which a logic signal a, a logic signal b and a control signal Sel are input to output the logic signal a or the logic signal b by controlling a value of the control signal Sel; the operation circuit comprises: a 1T1R array F, wherein the 1T1R array F includes one 1T1R device R, a word line signal corresponding to R is V_(WL), a bit line signal corresponding to R is V_(BL), and a source line signal corresponding to R is V_(SL).

In conjunction with the fifth aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:

(S4-1) Inputting logic signals V_(WL)=1, V_(BL)=a and V_(SL)=ā to initialize the 1T1R device R, and write the input logic signal an into R of the 1T1R array F.

(S4-2) Inputting logic signals V_(WL)=Sel, V_(BL)=b and V_(SL)=b to input the logic signal b and the control signal Sel so as to select an output logic signal out,

wherein the logic signal a and the logic signal b represent only two independent logic signals; when the control signal Sel=0, the output signal out=a; and when the control signal Sel=1, the output signal out=b.

According to a sixth aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a multi-bit carry select adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(0˜n−1) and carry information c₀, n represents the number of bits of the operation data, and in the calculation process, according to the carry information of each bit, an XNOR operation result or an XOR operation result of the corresponding bit of the operation data is selected as bit information of the sum; the operation circuit comprises: a 1T1R array G₁, a 1T1R array G₂ and a 1T1R array G₃; the 1T1R array G₁ includes n 1T1R devices R_(0x)˜R_((n−1)x) for calculating and storing XNOR operation results of data a_(0˜n−1) and b_(0˜n−1) (X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1)), word line control signals corresponding to R_(0x)˜R_((n−1)x) are respectively V_(WL0x)˜V_(WL(n−1)x), bit line control signals corresponding to R_(0x)˜R_((n−1)x) are respectively V_(BL0x)˜V_(BL(n−1)x), and source line control signals corresponding to R_(0x)˜R_((n−1)x) are respectively V_(SL0x)˜V_(SL(n−1)x); the 1T1R array G₂ includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculating carry data c_(i) (i is an integer from 0 to n), word line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(WL0x)˜V_(WLnc), bit line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), and source line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array G₃ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)-V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)-V_(SL(n−1)); and the XNOR operation results X_(0˜n−1) calculated by the 1T1R array G₁ and the carry information c_(i) calculated by the 1T1R array G₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array G₃ through the data transmission circuit.

In conjunction with the sixth aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:

(S5-1) Inputting logic signals V_(WL0x˜(n−1)x)=1, V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜7x)=b_(0˜n−1) to store the result b_(0˜n−1) of inverting the input operation data b_(0˜n−1) in R_(0x˜(n−1)x) of the 1T1R array G₁; inputting logic signals V_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to store c₀ in R_(0c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0c˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) , to store the input operational data a_(0˜n−1) in R_(0˜n−1) of the 1T1R array G₃.

(S5-2) Inputting logic signals V_(WL0x˜(n−1)x)=a_(0˜n−1), V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜(n−1)x)=b_(0˜n−1) to calculate XNOR operation results of the calculated data a_(0˜n−1) and b_(0˜n−1) (X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1)) and store X_(0˜n−1) in R_(0x˜(n−1)x) of the 1T1R array G₁; inputting logic signals V_(WL0c)=0, V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0x˜(n−1))=b_(0˜n−1), V_(BL0x˜(n−1))=a_(0˜n−1) and V_(SL0x˜(n−1))=a_(0˜n−1) , to calculate XOR operation results s_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* in R_(0˜n−1) of the 1T1R array G₃.

(S5-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜nc)=1, V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜(n−1))=0, V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s₀ and s₁, and store s₀ in R₀ of the 1T1R array G₃ and s₁ in R₁ of the 1T1R array G₃; when c₀=0, s₀=a₀⊕b₀, and when c₁=0, s₀=a₀⊕b₀ ; when c₁=0, s₁=a₁⊕b₁, and when c₁=1, s₁=a₁⊕b₁ .

(S5-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2.

(S5-5) Inputting logic signals V_(WL0c˜ic)=0, V_(WL(i+1)c˜nc)=1, V_(BL0c˜nc)=a_(i) and V_(SL0c˜nc)=b_(i) to calculate c_(i+1)=a_(i)·b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) in R_((i+1)c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0x˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1)=)0, V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s_(i) and store s_(i) in R_(i) of the 1T1R array G₃; when c_(i)=0, s_(i)=a_(i)⊕b_(i), and when c_(i)=1, s_(i)=a_(i)⊕b_(i) .

(S5-6) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S5-5); otherwise, proceeding to a step (S5-7).

(S5-7) Inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1, V_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array G₃; when n_(n−1)=0, s_(n−1)=a_(n−1)⊕b_(n−1), and when c_(n−1)=1, s₇=a_(n−1)⊕b_(n−1) .

According to a seventh aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a multi-bit pre-calculation adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(˜n−1) and carry information c₀, and n represents the number of bits of the operation data; the operation circuit comprises: a 1T1R array H₁ and a 1T1R array Hz; the 1T1R array H₁ includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculating carry data c_(i) (i is an integer from 0 to n), word line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(WL0c)˜V_(WLnc), bit line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), and source line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array H₂ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the carry information c_(i) calculated by the 1T1R array H₁ is converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array H₂ through the data transmission circuit.

In conjunction with the seventh aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:

(S6-1) Inputting logic signals V_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to store c₀ in R_(0c˜nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=c₀ and V_(SL0˜(n−1))=c₀ to store the input carry information c₀ in R_(0˜n−1) of the 1T1R array H₂.

(S6-2) Inputting logic signals V_(WL0c)=0, V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a₀, V_(SL0)=b₀ and V_(SL1˜(n−1))=b₀ to calculate s₀′=c₀·a₀+c₀ ·a₀·b₀ +c₀·a₀ ·b₀ and c₁=a₀·b₀+a₀·c₀+c₀·b₀, and store s₀′ in R₀ of the 1T1R array H₂ and c₁ in R_(1˜n−1) of the 1T1R array H₂.

(S6-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜nc)=1, V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜ne) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0)=b₀, V_(BL1˜(n−1))=a₁, V_(SL0)=c₁, V_(SL1)=b₁ and V_(SL2˜(n−1))=b₁ to calculate s₀=a₀⊕b₀⊕c₀, s₁′=c₁·a₁+c₁ ·a₁+b₁ +c₁·a₁ ·b₁ and c₂=a₁·b₁+a₁·c₁+c₁·b₁, and store s₀ in R₀ of the 1T1R array H₂, s₁′ in R₁ of the 1T1R array H₂ and c₂ in R₂˜R₇ of the 1T1R array H₂.

(S6-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=1.

(S6-5) Inputting logic signals V_(WL0c˜(i+2)c)=0, V_(WL(i+2)c˜nc)=1, V_(BL0c˜nc)=a_(i+1) and V_(SL0c˜nc)=b_(i+1) to calculate c_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c_(i+1)·b_(i+1) and store c_(i+2) in R_((i+2)c˜nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(i−1))=0, V_(WLi˜(n−1))=1, V_(BL0˜(i−1))=0, V_(BLi)=b_(i), V_(BL2˜7)=a_(i+1), V_(SL0˜(i˜1))=0, V_(SLi)=c_(i+1), V_(SL(i+1))=b_((i+1)) and V_(SL(i+2)˜(n−1))=b_(i+1) to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i), s_(i+1)′=c_(i+1)·a_(i+1)+c_(i+1) ·a_(i+1)·b_(i+1) +c_(i+1)·a_(i+1) ·b_(i+1) , and c_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c_(i+1)·b_(i+1) and store s_(i) in R_(i) of the 1T1R array H₂, s_(i+1)′ in R_(i+1) of the 1T1R array H₂ and c_(i+2) in R_((i+2)˜(n−1)) of the 1T1R array H₂.

(S6-6) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S6-5); otherwise, proceeding to a step (S6-7).

(S6-7) Inputting logic signals V_(WL0˜(n−1)c)=0, V_(WLnc)=1, V_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−3))=0, V_(WL(n−2)˜(n−1))=1, V_(BL0˜(n−3))=0, V_(BL(n−2))=b_(n−2), V_(BL(n−1))=a_(n−1), V_(SL0˜(n−3))=0, V_(SL(n−2))=c_(n−1) and V_(SL7)=b_(n−1) to calculate s_(n−2)=a_(n−2)⊕b_(n−2)⊕c_(n−2) and s_(n−1)′=c_(n−1)·a_(n−1)+c_(n−1) ·a_(n−1)·b_(n−1) +c_(n−1)·a_(n−1) ·b_(n−1) , and store s_(n−2) in R_(n−2) of the 1T1R array H₂ and s_(n−1)′ in R_(n−1) of the 1T1R array H₂.

(S6-8) Inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=1, V_(BL0˜(n−2))=0, V_(BL(n−1))=b_(n−1), V_(SL0˜(n−2))=0 and V_(SL(n−1))=c_(n) to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array H₂.

In general, with the above technical solution conceived by the present invention, a computing array based on 1T1R device is provided, and based on the computing array according to the present invention, multiple operation circuits are provided, which can achieve the following beneficial effects.

(1) The operation circuits are based on the computing array based on 1T1R device, and can directly store the calculated result in the 1T1R devices of the computing array while performing the logic operation, thereby achieving the fusion of computing and storage.

(2) The operation circuits according to the present invention can complete all logical operations in two steps when implementing 16 kinds of Boolean logic operations, greatly simplifying the design of the logic circuit and reducing the complexity of the integration process.

(3) By setting a different number of 1T1R arrays in the computing array and a different number of 1T1R devices in the 1T1R array in combination with the corresponding operating methods, in addition to 16 basic Boolean logic operations, complex operations such as a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a computing array based on 1T1R device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a 1T1R array in the computing array according to the embodiment of the present invention.

FIG. 3 is a schematic diagram of a three-dimensional structure and an equivalent circuit diagram of the 1T1R device according to the embodiment of the present invention, in which (a) is a schematic diagram of a three-dimensional structure of the 1T1R device; and (b) is an equivalent circuit diagram of a 1T1R device.

FIG. 4 is a block diagram and an equivalent circuit diagram of an operation circuit of a 1-bit full adder based on the computing array according to an embodiment of the present invention, in which (a) is a block diagram of the operation circuit of the 1-bit full adder; and (b) is an equivalent circuit diagram of the operation circuit of the 1-bit full adder.

FIG. 5 is an equivalent circuit diagram of an operation circuit of an 8-bit step-by-step carry adder based on the computing array according to an embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of an operation circuit of an optimized 8-bit step-by-step carry adder based on the computing array according to an embodiment of the present invention.

FIG. 7 is a block diagram and an equivalent circuit diagram of an operation circuit of a 2-bit data selector based on the computing array according to an embodiment of the present invention, in which (a) is a block diagram of the operation circuit of the 2-bit data selector; and (b) is an equivalent circuit diagram of the operation circuit of the 2-bit data selector.

FIG. 8 is an equivalent circuit diagram of an operation circuit of an 8-bit carry select adder based on the computing array according to an embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of an operation circuit of an 8-bit pre-calculation adder based on the computing array according to an embodiment of the present invention.

In all figures, the same elements or structures are denoted by the same reference numerals, in which:

100: source line decoder, 101: word line decoder, 102: bit line decoder, 103: signal amplifier, 104: state controller, 105: control signal modem, 106: data transmission circuit, 300: bit Line, 301: upper electrode of RRAM, 302: functional layer of RRAM, 303: lower electrode of RRAM, 304: source line, 305: gate of transistor, 306: insulating layer of transistor, 307: source of transistor, 308: drain of transistor, and 309: substrate of transistor.

DETAILED DESCRIPTION OF THE EMBODIMENTS

For clear understanding of the objectives, features and advantages of the present invention, detailed description of the present invention will be given below in conjunction with accompanying drawings and specific embodiments. It should be noted that the embodiments described herein are only meant to explain the present invention, and not to limit the scope of the present invention. Furthermore, the technical features related to the embodiments of the invention described below can be mutually combined if they are not found to be mutually exclusive.

A computing array based on 1T1R device according to the present invention, as shown in FIG. 1, includes: one or more 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R array.

The 1T1R array, as shown in FIG. 2, includes 1T1R devices arranged in an array, word lines WL, bit lines BL and source lines SL; the 1T1R devices realize storage and processing of information through different resistance states; the 1T1R devices in the same row are connected to the same bit line, and the 1T1R devices in the same column are connected to the same bit line and word line; and through applying different signals to the word lines WL, bit lines BL and source lines SL, different operations are achieved and operation results are stored.

The 1T1R device, as shown in FIG. 3, includes a transistor and a resistive element. The transistor includes a substrate 309, a source 307, a drain 308, an insulating layer 306 and a gate 305. In this embodiment, the resistive element is a resistive random access memory (RRAM), which includes: an upper electrode 301, a functional layer 302 and a lower electrode 303. The source 307 of the transistor is connected to the bit line 300, the gate 305 of the transistor is connected to the word line, the upper electrode 301 of RRAM is connected to the bit line 300, and the lower electrode 303 of RRAM is connected to the drain 308 of the transistor.

The resistance states of the 1T1R devices include: High Resistance H and Low Resistance L. The resistance state of the 1T1R device can be reversibly transformed under the stimulation of an applied signal, namely, with the stimulation of an applied signal, the resistance state of the 1T1R device can be transformed from High Resistance to Low Resistance, and with the stimulation of another applied signal, the resistance state of the 1T1R device can be transformed from Low Resistance to High Resistance. By using the two resistance states of the 1T1R device, storage and processing of information can be achieved.

As shown in FIG. 1, the peripheral circuit includes a state controller 104, a word line decoder 101, a source line decoder 100, a bit line decoder 102, a signal amplifier 103, a control signal modem 105 and a data transmission circuit 106, in which:

The state controller 104 has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result.

An input terminal of the word line decoder 101 is connected to the word line output terminal of the state controller 104, an output terminal of the word line decoder 101 is connected to the word line of the 1T1R array; the word line decoder 101 decodes the control signal generated by the state controller 104 to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array.

An input terminal of the bit line decoder 102 is connected to the bit line output terminal of the state controller 104, an output terminal of the bit line decoder 102 is connected to the bit line of the 1T1R array; the bit line decoder 102 decodes the control signal generated by the state controller 104 to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array.

An input terminal of the source line decoder 100 is connected to the source line output terminal of the state controller 104, an output terminal of the source line decoder 100 is connected to the source line of the 1T1R array; the source line decoder 100 decodes the control signal generated by the state controller 104 to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array.

The word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array.

An input terminal of the signal amplifier 103 is connected to the bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier 103 converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem 105.

A first input terminal of the control signal modem 105 is connected to the secondary output terminal of the state controller 104, a second input terminal of the control signal modem 105 is connected to an output terminal of the signal amplifier 103; the control signal modem 105 decodes the control signal generated by the state controller 104 to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier 103; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array.

An input terminal of the data transmission circuit 106 is connected to an output terminal of the control signal modem 105; the data transmission circuit 106 feeds back the data voltage signal output by the control signal modem 105 to the state controller 104 through the result input terminal of the state controller 104, or transmits the control signal output from the control signal modem 105 to a word line decoder, a bit line decoder and a source line decoder of the next-stage circuit.

The data input/output terminal Data, the address input terminal Address and the clock signal input terminal CLK of the state controller 104 respectively serve as a data input/output terminal, an address input terminal and a clock signal input terminal of the computing array.

In the computing array based on 1T1R device, applied voltage pulses are used as input signals to perform logic operation, and the result of the logic operation is characterized by the final resistance state of the 1T1R device; the result of the logic operation can be non-volatilely stored in the resistance state of the device, the resistance state can be read by a read signal of a small current (generally at the nanoampere level) or a small voltage (generally 0.2V or less), and the resistance signal can be erased by applying a voltage pulse with a certain amplitude and pulse width.

In the computing array based on 1T1R device, Boolean logic operations are achieved in the 1T1R devices by applying different voltage pulse signals to the word lines, source lines and bit lines of the 1T1R array. The initial resistance state of the 1T1R device is defined as a logic signal I, in which I=0 when the initial resistance state of the 1T1R device is High Resistance, and I=1 when the initial resistance state of the 1T1R device is Low Resistance; the word line level voltage is defined as a logic signal V_(WL), in which V_(WL)=0 when a zero-level pulse is applied to the word line, and V_(WL)=1 when a forward voltage pulse is applied to the word line; the bit line level voltage is defined as a logic signal V_(BL), in which V_(BL)=0 when a zero-level pulse is applied to the bit line, and V_(BL)=1 when a forward voltage pulse is applied to the bit line; the source line level voltage is defined as a logic signal V_(SL), in which V_(SL)=0 when a zero-level pulse is applied to the source line, and V_(SL)=1 when a forward voltage pulse is applied to the source line; the result of the logical operation in the 1T1R device is non-volatilely stored in the 1T1R device, and when information stored in the 1T1R device is read, the resistance state of the 1T1R device is defined as a logic signal R, in which R=0 when the resistance state of the 1T1R device is High Resistance, and R=1 when the resistance state of the 1T1R device is Low Resistance; and a logical relationship between the logic signal I, the logic signal V_(WL), the logic signal V_(BL), the logic signal V_(SL), and the logic signal R is:

R=I· V _(WL) +I·V _(WL) ·V _(BL) +I·V _(WL)· V _(BL) · V _(SL) +Ī·V _(WL) ·V _(BL)· V _(ST)

In the computing array based on 1T1R device, Boolean logic operation are implemented in a single 1T1R device, and specifically, the operating method includes the following steps.

(1) Initializing the 1T1R device to obtain a logic signal I.

(2) Respectively applying a voltage pulse signal to a word line, a source line and a bit line to obtain a logic signal V_(WL), a logic signal V_(SL) and a logic signal V_(BL).

(3) Reading a result of the logical operation, that is, a logic signal R.

By controlling values of the logic signals I, V_(WL), V_(BL) and V_(SL), the following 16 Boolean logic operations can be implemented:

implementation of logic 0: I=0, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of logic 1: I=1, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=0 and V_(SL)=q;

implementation of p logic: I=q, V_(WL)=0, V_(BL)=0 and V_(SL)=p;

implementation of p logic: I=p, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of q logic: I=q, V_(WL)=0, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=p, V_(WL)=1, V_(BL)=p and V_(SL)=0;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=0 and V_(SL)=q;

implementation of p·q logic: I=0, V_(WL)=p, V_(BL)=q and V_(SL)=0;

implementation of p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p+q logic: I=1, V_(WL)=1, V_(BL)=p and V_(SL)=q;

implementation of p+q logic: I=1, V_(WL)=p, V_(BL)=q and V_(SL)=1;

implementation of p·q logic: I=q, V_(WL)=1, V_(BL)=0 and V_(SL)=p;

implementation of p·q logic: I=p, V_(WL)=1, V_(BL)=0 and V_(SL)=q;

implementation of p·q+p·q logic: I=p, V_(WL)=q, V_(BL)=p and V_(SL)=p; and

implementation of p·q+p·q logic: I=q, V_(WL)=p, V_(BL)=q and V_(SL)=q.

Further, by inputting a logic signal V_(WL)=1 via the word line, a logic signal V_(BL)=V_(read) via the bit line and a logic signal V_(SL)=0 via the source line, the logic signal stored on the 1T1R device can be read, in which V_(read) is a voltage pulse signal applied when the resistance state of the 1T1R device is read.

In the present invention, symbols similar to I, V_(WL), V_(BL) and V_(SL) are used to denote logical signals with the same concept, and signals corresponding to different 1T1R devices are distinguished only by different subscripts.

FIG. 4 shows an operation circuit based on the computing array according to the present invention for implementing a 1-bit full adder, in which a sum s₀ and a high-order carry c₁ are calculated according to a logic signal a, a logic signal b and a low-order carry c₀ that are input; the operation circuit includes: a 1T1R array A₁, a 1T1R array A₂ and a 1T1R array A₃; the 1T1R array A₁ includes a 1T1R device R_(b) for calculating and storing intermediate data s₀*, a word line signal corresponding to R_(b) is V_(WLb), a bit line signal corresponding to R_(b) is V_(BLb) and a source line signal corresponding to R_(b) is V_(SLb); the 1T1R array A₂ includes a 1T1R device R_(c) for calculating and storing the high-order carry c₁, a word line signal corresponding to R_(c) is V_(WLc), a bit line signal corresponding to R_(c) is V_(BLc) and a source line signal corresponding to R_(c) is V_(SLc); the 1T1R array A₃ includes a 1T1R device R_(s) for calculating and storing the sum s₀, a word line signal corresponding to R_(s) is V_(WLs), a bit line signal corresponding to R_(s) is V_(BLs) and a source line signal corresponding to R_(s) is V_(SLs); and the intermediate data s₀* calculated by the 1T1R array A₁ and the high-order carry c₁ calculated by the 1T1R array A₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array A₃ through the data transmission circuit.

In conjunction with the operation circuit based on the computing array shown in FIG. 4, an operating method according to the present invention comprises the following steps.

(S1-1) Inputting logic signals V_(WLc)=1, V_(BLc)=c₀ and V_(SLc)=c₀ to write the input logic signal c₀ into R_(c) of the 1T1R array A₂; inputting logic signals V_(WLb)=1, V_(BLb)=a₀ and V_(SLb)=a₀ , to write the input logic signal a₀ into R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=1, V_(BLs)=a₀ and V_(SLs)=a₀ to write the input logic signal a₀ into R_(s) of the 1T1R array A₃.

(S1-2) Inputting logic signals V_(WLc)=1, V_(BLc)=a₀ and V_(SLc)=b₀ to calculate a high-order carry c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(c) of the 1T1R array A₂; inputting logic signals V_(WLb)=b₀, V_(BLb)=a₀ and V_(SLb)=a₀ to calculate an intermediate result s₀*=a₀⊕b₀ and store s₀* in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=b₀, V_(BLs)=a₀ and V_(SLs)=a₀ to calculate an intermediate result s₀* and store s₀* in R_(s) of the 1T1R array A₃.

(S1-3) reading the logic signal c₁ stored in R_(c) of the 1T1R array A₂; reading the logic signal s₀* stored in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=c₀, V_(BLs)=s₀* and V_(SLs)=s₀* to calculate a sum s₀=a₀⊕b₀⊕c₀ and store s₀ in R_(s) of the 1T1R array A₃.

(S1-4) reading the logic signal s₀ stored in R_(s) of the 1T1R array A₃.

FIG. 5 shows an operation circuit based on the computing array according to the present invention for implementing an 8-bit step-by-step carry adder, in which sums s_(0˜7) and carry information c₈ are calculated according to input data a_(0˜7) and b_(0˜7) and carry information c₀; the operation circuit includes: a 1T1R array D₁, a 1T1R array D₂ and a 1T1R array D₃; the 1T1R array D₁ includes eight 1T1R devices R_(0b)˜R_(7b) for calculating and storing intermediate results, word line control signals corresponding to R_(0b)˜R_(7b) are respectively V_(WL0b)˜V_(WL7b), bit line control signals corresponding to R_(0b)˜R_(7b) are respectively V_(BL0b)˜V_(BL7b), and source line control signals corresponding to R_(0b)˜R_(7b) are respectively V_(SL0b)˜V_(SL7b); the 1T1R array D₁ is used for data backup; the 1T1R array D₂ includes a 1T1R device R₈ for calculating and storing carry data c_(i) (i is an integer from 0 to 8), a word line control signal corresponding to R₈ is V_(WL8), a bit line control signal corresponding to R₈ is V_(BL8) and a source line control signal corresponding to R₈ is V_(SL8); the 1T1R array D₃ includes eight 1T1R devices R₀˜R₇ for calculating and storing addition operation results s_(0˜7), word line control signals corresponding to R₀˜R₇ are respectively V_(WL0)˜V_(WL7), bit line control signals corresponding to R₀˜R₇ are respectively V_(BL0)˜V_(BL7), and source line control signals corresponding to R₀˜R₇ are respectively V_(SL0)˜V_(SL7); and the intermediate data s_(0˜7)* calculated by the 1T1R array D₁ and the carry information c₁ calculated by the 1T1R array D₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array D₃ through the data transmission circuit.

In conjunction with the operation circuit based on the computing array shown in FIG. 5, an operating method according to the present invention comprises the following steps.

(S2-1) Inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=a_(0˜7) and V_(SL0˜7)=a_(0˜7) to write the input data a_(0˜7) into R₀˜R₇ of the 1T1R array D₃; inputting logic signals V_(WL8)=1, V_(BL8)=c₀ and V_(SL8)=c₀ to write the lower-order carry c₀ into R₈ of the 1T1R array D₂.

(S2-2) inputting logic signals V_(WL0˜7)=b_(0˜7), V_(BL0˜7)=a_(0˜7) and V_(SL0˜7)=a_(0˜7) to calculate intermediate results s_(0˜7)*=a_(0˜7)⊕b_(0˜7) and store s_(0˜7)* in R₀˜R₇ of the 1T1R array D₃; inputting logic signals V_(WL0b˜7b)=b_(0˜7), V_(BL0b˜7b)=a_(0˜7) and V_(SL0b˜7b)=a_(0˜7) to calculate intermediate results s_(0˜7)* and store s_(0˜7)* in R_(0b)˜R_(7b) of the 1T1R array D₁; inputting logic signals V_(WL8)=1, V_(BL8)=a₀ and V_(SL8)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R₈ of the 1T1R array D₂.

(S2-3) Reading s₀* from R_(0b) of the 1T1R array D₁, and reading s₁* from R_(ib) of the 1T1R array D₁; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜7)=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜7)=0, V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜7)=0 to calculate s₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array D₃ and s₁ in R₁ of the 1T1R array D₃.

(S2-4) Inputting logic signals V_(WL8)=1, V_(BL8)=a₁ and V_(SL8)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R₈ of the 1T1R array D₂.

(S2-5) Reading s₂* from R_(2b) of the 1T1R array D₁; inputting logic signals V_(WL0˜1)=0, V_(WL2)=c₂, V_(WL3˜7)=0, V_(BL0˜1)=0, V_(BL2)=s₂*, V_(BL3˜7)=0, V_(SL0˜1)=0, V_(SL2)=s₂* and V_(SL3˜7)=0 to calculate s₂=a₂⊕b₂⊕c₂ and store s₂ in R₂ of the 1T1R array D₃.

(S2-6) Inputting logic signals V_(WL8)=1, V_(BL8)=a₂ and V_(SL8)=b₂ to calculate c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store c₃ in R₈ of the 1T1R array D₂.

(S2-7) Reading s₃* from R_(3b) of the 1T1R array D₁; inputting logic signals V_(WL0˜2)=0, V_(WL3)=c₃, V_(WL4˜7)=0, V_(BL0˜2)=0, V_(BL3)=s₃*, V_(BL4˜7)=0, V_(SL0˜2)=0, V_(SL3)=s₃* and V_(SL4˜7)=0 to calculate s₃=a₃⊕b₃⊕c₃ and store s₃ in R₃ of the 1T1R array D₃.

(S2-8) inputting logic signals V_(WL8)=1, V_(BL8)=a₃ and V_(SL8)=b₃ to calculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ and store c₄ in R₈ of the 1T1R array D₂.

(S2-9) Reading s₄* from R_(4b) of the 1T1R array D₁; inputting logic signals V_(WL0˜3)=0, V_(WL4)=c₄, V_(WL5˜7)=0, V_(BL0˜3)=0, V_(BL4)=s₄*, V_(BL5˜7)=0, V_(SL0˜3)=0, V_(SL4)=s₄* and V_(SL5˜7)=0 to calculate s₄=a₄⊕b₄⊕c₄ and store s₄ in R₄ of the 1T1R array D₃.

(S2-10) Inputting logic signals V_(WL8)=1, V_(BL8)=a₄ and V_(SL8)=b₄ to calculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ and store c₅ in R₈ of the 1T1R array D₂.

(S2-11) Reading s₅* from R_(5b) of the 1T1R array D₁; inputting logic signals V_(WL0˜4)=0, V_(WL5)=c₅, V_(WL6˜7)=0, V_(BL0˜4)=0, V_(BL5)˜s₅*, V_(BL6˜7)=0, V_(SL0˜4)=0, V_(SL5)=s₅* and V_(SL6˜7)=0 to calculate s₅=a₅⊕b₅⊕c₅ and store s₅ in R₅ of the 1T1R array D₃.

(S2-12) Inputting logic signals V_(WL8)=1, V_(BL8)=a₅ and V_(SL8)=b₅ to calculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ and store c₆ in R₈ of the 1T1R array D₂.

(S2-13) Reading s₆* from R_(6b) of the 1T1R array D₁; inputting logic signals V_(WL0˜5)=0, V_(WL6)=c₆, V_(WL7)=0, V_(BL0˜5)=0, V_(BL6)=s₆*, V_(BL7)=0, V_(SL0˜5)=0, V_(SL6)=s₆* and V_(SL7)=0 to calculate s₆=a₆⊕b₆⊕c₆ and store s₆ in R₆ of the 1T1R array D₃.

(S2-14) Inputting logic signals V_(WL8)=1, V_(BL8)=a₆ and V_(SL8)=b₆ to calculate c₇=a₆·b₆+a₆·c₆+c₆·b₆ and store c₇ in R₈ of the 1T1R array D₂.

(S2-15) Reading s₇* from R_(7b) of the 1T1R array D₁; inputting logic signals V_(WL0˜6)=0, V_(WL7)=c₇, V_(BL0˜6)=0, V_(BL7)=s₇*, V_(SL0˜6)=0 and V_(SL7)=s₇* to calculate s₇=a₇⊕b₇⊕c₇ and store s₇ in R₇ of the 1T1R array D₃.

(S2-16) Inputting logic signals V_(WL8)=1, V_(BL8)=a₇ and V_(SL8)=b₇ to calculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ and store c₈ in R₈ of the 1T1R array D₂.

FIG. 6 shows an operation circuit based on the computing array according to the present invention for implementing an optimized 8-bit step-by-step carry adder, in which sums s_(0˜7) and carry information c₈ are calculated according to input data a_(0˜7) and b_(0˜7) and carry information c₀; the operation circuit includes: a 1T1R array E₁, a 1T1R array E₂ and a 1T1R array E₃; the 1T1R array E₁ includes eight 1T1R devices R_(0b)˜R_(7b) for calculating and storing data s_(0˜7)*, word line control signals corresponding to R_(0b)˜R_(7b) are respectively V_(WL0b)˜V_(WL7b), bit line control signals corresponding to R_(0b)˜R_(7b) are respectively V_(BL0b)˜V_(BL7b), and source line control signals corresponding to R_(0b)˜R_(7b) are respectively V_(SL0b)˜V_(SL7b); the 1T1R array E₁ is used for data backup; the 1T1R array E₂ includes nine 1T1R devices R_(0c)˜R_(8c) for calculating and storing carry data c_(i) (i is an integer from 0 to 8), word line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(WL0c)˜V_(WL8c), bit line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(BL0c)˜V_(BL8c), and source line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(SL0c)˜V_(SL8c); the 1T1R array E₃ includes eight 1T1R devices R₀˜R₇ for calculating and storing addition operation results s_(0˜7); and the intermediate data s_(0˜7)* calculated by the 1T1R array E₁ and the carry information c_(i) calculated by the 1T1R array E₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array E₃ through the data transmission circuit.

In conjunction with the operation circuit based on the computing array shown in FIG. 6, an operating method according to the present invention comprises the following steps.

(S3-1) inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=a_(0˜7) and V_(SL0˜7)=a_(0˜7) to write the input operational data a_(0˜7) into R₀˜R₇ of the 1T1R array E₃; inputting logic signals V_(WL0b˜7b)=1, V_(BL0b˜7b)=a_(0˜7) and V_(SL0b˜7b)=a_(0˜7) to write the input operational data a_(0˜7) into R_(0b)˜R_(7b) of the 1T1R array E₁; inputting logic signals V_(WL0c˜8c)=1, V_(BL0c˜8)=c₀ and V_(SL0c˜8c)=c₀ to write the carry information c₀ into R_(0c)˜R_(8c) of the 1T1R array E₂.

(S3-2) Inputting logic signals V_(WL0˜7)=b_(0˜7), V_(BL0˜7)=a_(0˜7) and V_(SL0˜7)=a_(0˜7) to calculate intermediate results s_(0˜7)*=a_(0˜7)⊕b_(0˜7) and store s_(0˜7)* in R₀˜R₇ of the 1T1R array E₃; inputting logic signals V_(WL0b˜7b)=b_(0˜7), V_(BL0b˜7b)=a_(0˜7) and V_(SL0b˜7b)=a_(0˜7) to calculate intermediate results s_(0˜7)* and store s_(0˜7)* in R_(0b)˜R_(7b) of the 1T1R array E₁; inputting logic signals V_(WL0c)=0, V_(WL1c˜8c)=1, V_(BL0c˜8c)=a₀ and V_(SL0c˜8c)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜8c) of the 1T1R array E₂.

(S3-3) Reading s₀* from R_(0b) of the 1T1R array E₁, and reading s₁* from R_(1b) of the 1T1R array E1; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜7)=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜7)=0, V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜7)=0 to calculate s₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array E₃ and s₁ in R₁ of the 1T1R array E₃; inputting logic signals V_(WL0˜1c)=0, V_(WL2c˜8c)=1, V_(BL0c˜8c)=a₁ and V_(SL0c˜8c)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜8c) of the 1T1R array E₂.

(S3-4) Reading s₂* from R_(2b) of the 1T1R array E₁; inputting logic signals V_(WL0˜1)=0, V_(WL2)=c₂, V_(WL3˜7)=0, V_(BL0˜1)=0, V_(BL2)=s₂*, V_(BL3˜7)=0, V_(SL0˜1)=0, V_(SL2)=s₂* and V_(SL3˜7)=0 to calculate s₂=a₂⊕b₂⊕c₂, and store s₂ in R₂ of the 1T1R array E₃; inputting logic signals V_(WL0˜2c)=0, V_(WL3c˜8c)=1, V_(BL0c˜8c)=a₂ and V_(SL0c˜8c)=b₂ to calculate c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store c₃ in R_(3c˜8c) of the 1T1R array E₂.

(3-5) Reading s₃* from R_(3b) of the 1T1R array E₁; inputting logic signals V_(WL0˜2)=0, V_(WL3)=c₃, V_(WL4˜7)=0, V_(BL0˜2)=0, V_(BL3)=s₃*, V_(BL4˜7)=0, V_(SL0˜2)=0, V_(SL3)=s₃* and V_(SL4˜7)=0 to calculate s₃=a₃⊕b₃⊕c₃ and store s₃ in R₃ of the 1T1R array D₃; inputting logic signals V_(WL0c˜3c)=0, V_(WL4c˜8c)=1, V_(BL0c˜8c)=a₃ and V_(SL0c˜8c)=b₃ to calculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ and store c₄ in R_(4c˜8c) of the 1T1R array E₂.

(3-6) Reading s₄* from R_(4b) of the 1T1R array E₁; inputting logic signals V_(WL0˜3)=0, V_(WL4)=c₄, V_(WL5˜7)=0, V_(BL0˜3)=0, V_(BL4)=s₄*, V_(BL5˜7)=0, V_(SL0˜3)=0, V_(SL4)=s₄* and V_(SL5˜7)=0 to calculate s₄=a₄⊕b₄⊕c₄ and store s₄ in R₄ of the 1T1R array E₃; inputting logic signals V_(WL0c˜4c)=0, V_(WL5c˜8c)=1, V_(BL0c˜8c)=a₄ and V_(SL0c˜8c)=b₄ to calculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ and store c₅ in R_(5c˜8c) of the 1T1R array E₂.

(3-7) Reading s₅* from R_(5b) of the 1T1R array E₁; inputting logic signals V_(WL0˜4)=0, V_(WL5)=c₅, V_(WL6˜7)=0, V_(BL0˜4)=0, V_(BL5)˜s₅*, V_(BL6˜7)=0, V_(SL0˜4)=0, V_(SL5)=s₅* and V_(SL6˜7)=0 to calculate s₅=a₅⊕b₅⊕c₅ and store s₅ in R₅ of the 1T1R array E₃; inputting logic signals V_(WL0˜5c)=1, V_(WL6c˜8c)=1, V_(BL0c˜8c)=a₅ and V_(SL0c˜8c)=b₅ to calculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ and store c₆ in R_(6c˜8c) of the 1T1R array E₂.

(3-8) Reading s₆* from R_(6b) of the 1T1R array E₁; inputting logic signals V_(WL0˜5)=0, V_(WL6)=c₆, V_(WL7)=0, V_(BL0˜5)=0, V_(BL6)=s₆*, V_(BL7)=0, V_(SL0˜5)=0, V_(SL6)=s₆* and V_(SL7)=0 to calculate s₆=a₆⊕b₆⊕c₆ and store s₆ in R₆ of the 1T1R array E₃; inputting logic signals V_(WL7c˜8c)=1, V_(BL0c˜8c)=a₆ and V_(SL0c˜8c)=b₆ to calculate c₇=a₆·b₆+a₆·c₆+c₆·b₆ and store c₇ in R_(7c˜8c) of the 1T1R array E₂.

(3-9) Reading s₇* from R_(7b) of the 1T1R array E₁; inputting logic signals V_(WL0˜6)=0, V_(WL7)=c₇, V_(BL0˜6)=0, V_(BL7)=s₇*, V_(SL0˜6)=0 and V_(SL7)=s₅* to calculate s₇=a₇⊕b₇⊕c₇ and store s₇ in R₇ of the 1T1R array E₃; and inputting logic signals V_(WL0˜7c)=0, V_(WL8c)=1, V_(BL0c˜8c)=a₇ and V_(SL0c˜8c)=b₇ to calculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ and store c₈ in R_(8c) of the 1T1R array E₂.

FIG. 7 shows an operation circuit based on the computing array according to the present invention for implementing a 2-bit data selector, in which a logic signal a, a logic signal b and a control signal Sel are input to output the logic signal a or the logic signal b by controlling a value of the control signal Sel; and the operation circuit includes a 1T1R array F, and the 1T1R array F includes one 1T1R device R.

In conjunction with the operation circuit based on the computing array shown in FIG. 7, an operating method according to the present invention comprises the following steps.

(S4-1) Inputting logic signals V_(WL)=1, V_(BL)=a and V_(SL)=ā to initialize the 1T1R device R, and write the input logic signal a into R of the 1T1R array F.

(S4-2) inputting logic signals V_(WL)=Sel, V_(BL)=b and V_(SL)=b to input the logic signal b and the control signal Sel so as to select an output logic signal out,

wherein the logic signal a and the logic signal b represent only two independent logic signals; when the control signal Sel=0, the output signal out=a; and when the control signal Sel=1, the output signal out=b.

FIG. 8 shows an operation circuit based on the computing array according to the present invention for implementing an 8-bit carry select adder, in which sums s_(0˜7) and carry information c₈ are calculated according to input data a_(0˜7) and b_(0˜7) and carry information c₀, and in the calculation process, according to the carry information of each bit, an XNOR operation result or an XOR operation result of the corresponding bit of the operation data is selected as bit information of the sum; the operation circuit includes a 1T1R array G₁, a 1T1R array G₂ and a 1T1R array G₃; the 1T1R array G₁ includes eight 1T1R devices R_(0x)˜R_(7x) for calculating and storing XNOR operation results of data a_(0˜7) and b_(0˜7) (X_(0˜7)=a_(0˜7) XNOR b_(0˜7)), word line control signals corresponding to R_(0x)˜R_(7x) are respectively V_(WL0x)˜V_(WL7x), bit line control signals corresponding to R_(0x)˜R_(7x) are respectively V_(BL0x)˜V_(BL7x), and source line control signals corresponding to R_(0x)˜R_(7x) are respectively V_(SL0x)˜V_(SL7x); the 1T1R array G₂ includes nine 1T1R devices R_(0c)˜R_(8c) for calculating carry data c_(i) (i is an integer from 0 to 8), word line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(WL0c)˜V_(WL8c), bit line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(BL0c)˜V_(BL8c), and source line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(SL0c)˜V_(SL8c); the 1T1R array G₃ includes eight 1T1R devices R₀˜R₇ for calculating and storing addition operation results s_(0˜7), word line control signals corresponding to R₀˜R₇ are respectively V_(WL0)˜V_(WL7), bit line control signals corresponding to R₀˜R₇ are respectively V_(BL0)˜V_(BL7), and source line control signals corresponding to R₀˜R₇ are respectively V_(SL0)˜V_(SL7); and the XNOR operation results X_(0˜7) calculated by the 1T1R array G₁ and the carry information c_(i) calculated by the 1T1R array G₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array G₃ through the data transmission circuit.

In conjunction with the operation circuit based on the computing array shown in FIG. 8, an operating method according to the present invention comprises the following steps.

(S5-1) Inputting logic signals V_(WL0x˜7x)=1, V_(BL0x˜7x)=b_(0˜7) and V_(SL0x˜7X)=b_(0˜7) to store the result b_(0˜7) of inverting the input operation data b_(0˜n−1) in R_(0x)˜R_(7x) of the 1T1R array G1; inputting logic signals V_(WL0c˜8c)=1, V_(BL0c˜8c)=c₀ and V_(SL0c˜8c)=c₀ to store c₀ in R_(0c)˜R_(8c), of the 1T1R array G₂; inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=a_(0˜7) and V_(SL0˜7)=a_(0˜7) to store the input operational data a_(0˜7) in R₀˜R₇ of the 1T1R array G₃.

(S5-2) Inputting logic signals V_(WL0x˜7x)=a_(0˜7); V_(BL0x˜7x)=b_(0˜7) and V_(SL0x˜7x)=b_(0˜7) to calculate XNOR operation results X_(0˜7)=a_(0˜7) XNOR b_(0˜7) of the calculated data a_(0˜7) and a_(0˜7) and store X_(0˜7) in R_(0x)˜R_(7x) of the 1T1R array G₁; inputting logic signals V_(WL1c˜8c)=1, V_(BL1c˜8c)=a₀ and V_(SL0c˜8c)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜7)=b_(0˜7), V_(BL0˜7)=a_(0˜7) and V_(SL0˜7)=a_(0˜7) to calculate XNOR operation results X_(0˜7) of the calculated data a_(0˜7) and b_(0˜7) and store X_(0˜7) in R₀˜R₇ of the 1T1R array G₃.

(S5-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜8c)=1, V_(BL0c˜8c)=a₁ and V_(SL0c˜8c)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜8c) of the 1T1R array G₂; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜7)=0, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₀ and s₁ and store s₀ in R₀ of the 1T1R array G₃ and s₁ in R₁ of the 1T1R array G₃; when c₀=0, s₀=a₀⊕b₀, and when c₁=0, s₀=a₀⊕b₀ ; when c₁=0, s₁=a₁⊕b₁, and when c₁=1, s₁=a₁⊕b₁ .

(S5-4) Inputting logic signals V_(WL0c˜2c)=0, V_(WL3c˜8c)=1, V_(BL0c˜8c)=a₂ and V_(SL0c˜8c)=b₂ to calculate c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store c₃ in R_(3c˜8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜1)=0, V_(WL2)=c₂, V_(WL3˜7)=0, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₂ and store s₂ in R₂ of the 1T1R array G₃; when c₂=0, s₂=a₂⊕b₂, and when c₂=1, s₂=s₂=a₂⊕b₂ .

(S5-5) Inputting logic signals V_(WL0c˜3c)=0, V_(WL4c˜8c)=1, V_(BL0c˜8c)=a₃ and V_(SL0c˜8c)=b₃ to calculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ and store c₄ in R_(4c˜8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜2)=0, V_(WL3)=c₃, V_(WL4˜7)=0, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₃ and store s₃ in R₃ of the 1T1R array G₃; when c₃=0, s₃=a₃⊕b₃, and when c₃=1, s₃=a₃⊕b₃ .

(S5-6) Inputting logic signals V_(WL0c˜4c)=0, V_(WL5c˜8c)=1, V_(BL0c˜8c)=a₄ and V_(SL0c˜8c)==b₄ to calculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ and store c₅ in R_(5c˜8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜3)=0, V_(WL3)=c₄, V_(WL5˜7)=0, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₄ and store s₄ in R₄ of the 1T1R array G₃; when c₄=0, s₄=a₄⊕b₄, and when c₄=1, s₄=a₄⊕b₄ .

(S5-7) Inputting logic signals V_(WL0c˜5c)=0, V_(WL6c˜8c)=1, V_(BL0c˜8c)=a₅ and V_(SL0c˜8c)==b₅ to calculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ and store c₆ in R_(6c˜8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜4)=0, V_(WL5)=c₅, V_(WL6˜7)=0, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₅ and store s₅ in R₅ of the 1T1R array G₃; when c₅=0, s₅=a₅⊕b₅, and when c₅=1, s₅=a₅⊕b₅ .

(S5-8) Inputting logic signals V_(WL0c˜6c)=0, V_(WL7c˜8c)=1, V_(BL0c˜8c)=a₆ and V_(SL0c˜8c)==b₆ to calculate c₇=a₆·b₆+a₆·c₆+c₆·b₆ and store c₇ in R_(7c˜8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜5)=0, V_(WL6)=c₆, V_(WL7)=0, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₆ and store s₆ in R₆ of the 1T1R array G₃; when c₆=0, s₆=a₆⊕b₆, and when c₅=1, s₆=a₆⊕b₆ .

(S5-9) Inputting logic signals V_(WL0c˜7c)=0, V_(WL8c)=1, V_(BL0c˜8c)=a₇ and V_(SL0c˜8c)==b₇ to calculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ and store c₈ in R_(8c) of the 1T1R array G₂; inputting logic signals V_(WL0˜6)=0, V_(WL7)=c₇, V_(BL0˜7)=X_(0˜7) and V_(SL0˜7)=X_(0˜7) to calculate s₇ and store s₇ in R₇ of the 1T1R array G₃; when c₇=0, s₇=a₇⊕b₇, and when c₇=1, s₇=a₇⊕b₇ .

FIG. 9 shows an operation circuit based on the computing array according to the present invention for implementing an 8-bit pre-calculation adder, in which sums s_(0˜7) and carry information c₈ are calculated according to input data a_(0˜7) and b_(0˜7) and carry information c₀; the operation circuit includes a 1T1R array H₁ and a 1T1R array Hz; the 1T1R array H₁ includes nine 1T1R devices R_(0c)˜R_(8c) for calculating carry data c_(i) (i is an integer from 0 to 8), word line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(WL0c)˜V_(WL8c), bit line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(BL0c)˜V_(BL8c), and source line control signals corresponding to R_(0c)˜R_(8c) are respectively V_(SL0c)˜V_(SL8c); the 1T1R array H₂ includes eight 1T1R devices R₀˜R₇ for calculating and storing addition operation results s_(0˜7), word line control signals corresponding to R₀˜R₇ are respectively V_(WL0)˜V_(WL7), bit line control signals corresponding to R₀˜R₇ are respectively V_(BL0)˜V_(BL7), and source line control signals corresponding to R₀˜R₇ are respectively V_(SL0)˜V_(SL7); and the carry information c₁ calculated by the 1T1R array H₁ is converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array H₂ through the data transmission circuit.

In conjunction with the operation circuit based on the computing array shown in FIG. 9, an operating method according to the present invention comprises the following steps.

(S6-1) Inputting logic signals V_(WL0c˜8c)=1, V_(BL0c˜8c)=c₀ and V_(SL0c˜8c)=c₀ to store c₀ in R_(0c)˜R_(8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=c₀ and V_(SL0˜7)=c₀ to store the input carry information c₀ in R₀˜R₇ of the 1T1R array H₂.

(S6-2) Inputting logic signals V_(WL0c)=0, V_(WL1c˜8c)=1, V_(BL0c˜8c)=a₀ and V_(SL0c˜8c)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜7)=1, V_(BL0˜7)=a₀, V_(SL0)=b₀ and V_(SL1˜7)=b₀ to calculate s₀′=c₀·a₀+c₀ ·a₀·b₀ +c₀·a₀ ·b₀ and c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store s₀′ in R₀ of the 1T1R array H₂ and c₁ in R₁˜R₇ of the 1T1R array H₂.

(S6-3) Inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜8c)=1, V_(BL0c˜8c)=a₁ and V_(SL0c˜8c)=b₁ to calculate c₂=a₁˜b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜7)=1, V_(BL0)=b₀, V_(BL1˜7)=a₁, V_(SL0)=c₁, V_(SL1)=b₁ and V_(SL2˜7)=b₁ to calculate s₀=a₀⊕b₀⊕c₀, s₁′=c₁·a₁+c₁ ·a₁·b₁ +c₁·a₁ ·b₁ and c₂ and store s₀ in R₀ of the 1T1R array H₂, s₁′ in R₁ of the 1T1R array H₂ and c₁ in R₂˜R₇ of the 1T1R array H₂.

(S6-4) Inputting logic signals V_(WL0c˜2c)=0, V_(WL3c˜8c)=1, V_(BL0c˜8c)=a₂ and V_(SL0c˜8c)=b₂ to calculate c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store c₃ in R_(3c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0)=0, V_(WL1˜7)=1, V_(BL0)=0, V_(BL1)=b₁, V_(BL2˜7)=a₂, V_(SL0)=0, V_(SL0)=c₂, V_(SL2)=b₂ and V_(SL3˜7)=b₂ to calculate s₁=a₁⊕b₁⊕c₁, s₂′=c₂·a₂+c₂ ·a₂·b₂ +c₂·a₂ ·b₂ and c₃=a₂·b₂+a₂·c₂+c₂·b₂ and store s₁ in R₁ of the 1T1R array H₂, s₂′ in R₂ of the 1T1R array H₂ and c₂ in R₃˜R₇ of the 1T1R array H₂.

(S6-5) Inputting logic signals V_(WL0c˜3c)=0, V_(WL4c˜8c)=1, V_(BL0c˜8c)=a₃ and V_(SL0c˜8c)=b₃ to calculate c₄=a₃·b₃+a₃·c₃+c₃·b₃ and store c₄ in R_(4c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜1)=0, V_(WL2˜7)=1, V_(BL0˜1)=0, V_(BL2)=b₂, V_(BL3˜7)=a₃, V_(SL0˜1)=0, V_(SL2)=c₃, V_(SL3)=b₃ and V_(SL4˜7)=b₃ to calculate s₂=a₂⊕b₂⊕c₂, s₃′=c₃·a₃+c₃ ·a₃·b₃ +c₃·a₃ ·b₃ and c₄, and store s₂ in R₂ of the 1T1R array H₂, s₃′ in R₃ of the 1T1R array H₂ and c₄ in R₄˜R₇ of the 1T1R array H₂.

(S6-6) Inputting logic signals V_(WL0c˜4c)=0, V_(WL5c˜8c)=1, V_(BL0c˜8c)=a₄ and V_(SL0c˜8c)=b₄ to calculate c₅=a₄·b₄+a₄·c₄+c₄·b₄ and store c₅ in R_(5c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜2)=0, V_(WL3˜7)=1, V_(BL0˜2)=0, V_(BL3)=b₃, V_(BL4˜7)=a₄, V_(SL0˜2)=0, V_(SL3)=c₄, V_(SL4)=b₄ and V_(SL5˜7)=b₄ to calculate s₃=a₃⊕b₃⊕c₃, s₄′=c₄·a₄+c₄ ·a₄·b₄ +c₄·a₄ ·b₄ and c₅, and store s₃ in R₃ of the 1T1R array H₂, s₄′ in R₄ of the 1T1R array H₂ and c₅ in R₅˜R₇ of the 1T1R array H₂.

(S6-7) Inputting logic signals V_(WL0c˜5c)=0, V_(WL6c˜8c)=1, V_(BL0c˜8c)=a₅ and V_(SL0c˜8c)=b₅ to calculate c₆=a₅·b₅+a₅·c₅+c₅·b₅ and store c₆ in R_(6c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜3)=0, V_(WL4˜7)=1, V_(BL0˜3)=0, V_(BL4)=b₄, V_(BL5˜7)=a₅, V_(SL0˜3)=0, V_(SL4)=c₅, V_(SL5)=b₅ and V_(SL6˜7)=b₅ to calculate s₄=a₄⊕b₄⊕c₄, s₅′=c₅·a₅+c₅ ·a₅·b₅ +c₅·a₅ ·b₅ and c₆, and store s₄ in R₄ of the 1T1R array H₂, s₅′ in R₅ of the 1T1R array H₂ and c₆ in R₆˜R₇ of the 1T1R array H₂.

(S6-8) Inputting logic signals V_(WL0c˜6c)=0, V_(WL7c˜8c)=1, V_(BL0c˜8c)=a₆ and V_(SL0c˜8c)=b₆ to calculate c₇=a₆·b₆+a₆·c₆+c₆·b₆ and store c₇ in R_(7c˜8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜4)=0, V_(WL5˜7)=1, V_(BL0˜4)=0, V_(BL5)=b₅, V_(BL6˜7)=a₆, V_(SL0˜4)=0, V_(SL5)=c₆, V_(SL6)=b₆ and V_(SL7)=b₆ to calculate s₅=a₅⊕b₅⊕c₅, s₆′=c₆·a₆+c₆ ·a₆·b₆ +c₆·a₆ ·b₆ and c₇, and store s₅ in R₅ of the 1T1R array H₂, s₆′ in R₆ of the 1T1R array H₂ and c₇ in R₇ of the 1T1R array H₂.

(S6-9) Inputting logic signals V_(WL0c˜7c)=0, V_(WL8c)=1, V_(BL0c˜8c)=a₇ and V_(SL0c˜8c)=b₇ to calculate c₈=a₇·b₇+a₇·c₇+c₇·b₇ and store c₈ in R_(8c) of the 1T1R array H₁; inputting logic signals V_(WL0˜5)=0, V_(WL6˜7)=1, V_(BL0˜5)=0, V_(BL6)=b₆, V_(BL7)=a₇, V_(SL0˜5)=0, V_(SL6)=c₇ and V_(SL7)=b₇ to calculate s₆=a₆⊕b₆⊕c₆ and s₇′=c₇·a₇+c₇ ·a₇·b₇ +c₇·a₇ ·b₇ , and store s₆ in R₆ of the 1T1R array H₂ and s₇′ in R₇ of the 1T1R array H₂.

(S6-10) Inputting logic signals V_(WL0˜6)=0, V_(WL7)=1, V_(BL0˜6)=0, V_(BL7)=b₇, V_(SL0˜6)=0 and V_(SL7)=c₈, and inputting a logic signal of 0 to each of other terminals to calculate s₇=a₇⊕b₇⊕c₇ and store s₇ in R₇ of the 1T1R array H₂.

It should be readily understood to those skilled in the art that the above description is only preferred embodiments of the present invention, and does not limit the scope of the present invention. Any change, equivalent substitution and modification made without departing from the spirit and scope of the present invention should be included within the scope of the protection of the present invention. 

1. A computing array based on 1T1R device, comprising: one or more 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays.
 2. The computing array based on 1T1R device according to claim 1, wherein the 1T1R array includes 1T1R devices arranged in an array, word lines WL, bit lines BL and source lines SL; resistance states of the 1T1R devices include: High Resistance H and Low Resistance L; the 1T1R devices realize storage and processing of information through different resistance states; and the 1T1R devices in the same row are connected to the same word line, the 1T1R devices in the same column are connected to the same bit line and source line, and through applying different signals to the word lines WL, the bit lines BL and the source lines SL, different operations are achieved and operation results are stored.
 3. The computing array based on 1T1R device according to claim 2, wherein the 1T1R device includes a transistor and a resistive element; the transistor includes a substrate, a source, a drain, an insulating layer and a gate, in which the source is connected to the source line SL, and the gate is connected to the word line WL; the resistive element includes two end electrodes, one of which is connected to the bit line BL and the other of which is connected to the drain of the transistor; and the resistive element has a stacked structure with a nonvolatile resistance transition characteristic.
 4. The computing array based on 1T1R device according to claim 1, wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit; the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result; an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array; an input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to the bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array; an input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to the source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array; the word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array; an input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem; a first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array; an input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.
 5. The computing array based on 1T1R device according to claim 4, wherein the data input/output terminal Data, the address input terminal Address and the clock signal input terminal CLK of the state controller respectively serve as a data input/output terminal, an address input terminal and a clock signal input terminal of the computing array.
 6. The computing array based on 1T1R device according to claim 1, wherein 16 basic Boolean logic operations are implemented by controlling initial resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals; a logic signal stored in the 1T1R device is read by inputting a logic signal V_(WL)=1 via a word line, a logic signal V_(BL)=V_(read) via a bit line and a logic signal V_(SL)=0 via a source line; V_(read) is a voltage pulse signal applied when a resistance state of the 1T1R device is read.
 7. An operation circuit based on the computing array according to claim 4 for implementing a 1-bit full adder, in which a sum s₀ and a high-order carry c₁ are calculated according to a logic signal a, a logic signal b and a low-order carry c₀ that are input, comprising: a 1T1R array A₁, a 1T1R array A₂ and a 1T1R array A₃; the 1T1R array A₁ includes a 1T1R device R_(b) for calculating and storing intermediate data s₀*, a word line signal corresponding to R_(b) is V_(WLb), a bit line signal corresponding to R_(b) is V_(BLb) and a source line signal corresponding to R_(b) is V_(SLb); the 1T1R array A₂ includes a 1T1R device R_(c) for calculating and storing the high-order carry c₁, a word line signal corresponding to R_(c) is V_(WLc), a bit line signal corresponding to R_(c) is V_(BLc) and a source line signal corresponding to R_(c) is V_(SLc); the 1T1R array A₃ includes a 1T1R device R_(s) for calculating and storing the sum s₀, a word line signal corresponding to R_(s) is V_(WLs), a bit line signal corresponding to R_(s) is V_(BLs) and a source line signal corresponding to R_(s) is V_(SLs); and the intermediate data s₀* calculated by the 1T1R array A₁ and the high-order carry c₁ calculated by the 1T1R array A₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array A₃ through the data transmission circuit.
 8. An operating method based on the operation circuit according to claim 7, comprising: (S1-1) inputting logic signals V_(WLc)=1, V_(BLc)=c₀ and V_(SLc)=c₀ to write the input logic signal c₀ into R_(c) of the 1T1R array A₂; inputting logic signals V_(WLb)=1, V_(BLb)=a₀ and V_(SLb)=a₀ to write the input logic signal a₀ into R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=1, V_(BLs)=a₀ and V_(SLs)=a₀ to write the input logic signal a₀ into R_(s) of the 1T1R array A₃; (S1-2) inputting logic signals V_(WLc)=1, V_(BLc)=a₀ and V_(SLc)=b₀ to calculate a high-order carry c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(c) of the 1T1R array A₂; inputting logic signals V_(WLb)=b₀, V_(BLb)=a₀ and V_(SLb)=a₀ to calculate an intermediate result s₀*=a₀⊕b₀ and store s₀* in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=b₀, V_(BLs)=a₀ and V_(SLs)=a₀ to calculate an intermediate result s₀* and store s₀* in R_(s) of the 1T1R array A₃; (S1-3) reading the logic signal c₁ stored in R_(c) of the 1T1R array A₂; reading the logic signal s₀* stored in R_(b) of the 1T1R array A₁; inputting logic signals V_(WLs)=c₀, V_(BLs)=s₀* and V_(SLs)=s₀*, to calculate a sum s₀=a₀⊕b₀⊕c₀ and store s₀ in R_(s) of the 1T1R array A₃; and (S1-4) reading the logic signal s₀ stored in R_(s) of the 1T1R array A₃.
 9. An operation circuit based on the computing array according to claim 4 for implementing a multi-bit step-by-step carry adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(0˜n−1) and carry information c₀, and n represents the number of bits of the operation data, comprising: a 1T1R array D₁, a 1T1R array D₂ and a 1T1R array D₃; the 1T1R array D₁ includes n 1T1R devices R_(0b)˜R_((n−1)b) for calculating and storing intermediate results s_(0˜n−1)*, word line control signals corresponding to R_(0b)˜R_((n−1)b), are respectively V_(WL0b)˜V_(WL(n−1)b), bit line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(BL0b)˜V_(BL(n−1)b), and source line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(SL0b)˜V_(SL(n−1)b); the 1T1R array D₁ is used for data backup; the 1T1R array D₂ includes a 1T1R device R_(n) for calculating and storing carry data c_(i), i is an integer from 0 to 8, a word line control signal corresponding to R_(n) is V_(WLn), a bit line control signal corresponding to R_(n) is V_(BLn) and a source line control signal corresponding to R_(n) is V_(SLn); the 1T1R array D₃ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the intermediate data s_(0˜n−1)* calculated by the 1T1R array D₁ and the carry information c_(i) calculated by the 1T1R array D₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array D₃ through the data transmission circuit.
 10. An operating method based on the operation circuit according to claim 9, comprising: (S2-1) inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to write the input data a_(0˜n−1) into R_(0˜n−1) of the 1T1R array D₃; inputting logic signals V_(WLn)=1, V_(BLn)=c₀ and V_(SLn)=c₀ to write the carry information c₀ into R_(n) of the 1T1R array D₂, a word line input signal, a bit line input signal and a source line input signal of the 1T1R array D₁ being the same as that of the 1T1R array D₃; (S2-2) inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to calculate intermediate results s_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* in R_(0˜n−1) of the 1T1R array D₃; inputting logic signals V_(WL0b˜(n−1)b)=b_(0˜n−1), V_(BL0b˜(n−1))=a_(0˜n−1) and V_(SL0b˜(n−1)b)=a_(0˜n−1) to calculate intermediate results s_(0*n−1)* and store s_(0˜n−1) in R_(0b˜(n−1)b) of the 1T1R array D₁; inputting logic signals V_(WLn)=1, V_(BLn)=a₀ and V_(SLn)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(n) of the 1T1R array D₂; (S2-3) reading s₀* from R_(0b) of the 1T1R array D₁, and reading s₁* from R_(1b) of the 1T1R array D1; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜n−1)=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜n−1)=0, V_(SL0)=s₀*, V_(SL1)=s₁* and V_(SL2˜n−1)=0 to calculate s₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array D₃ and s₁ in R₁ of the 1T1R array D₃; (S2-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2; (S2-5) inputting logic signals V_(WLn)=1, V_(BLn)=a_(i−1) and V_(SLn)=b_(i−1) to calculate c_(i)=a_(i−1)·b_(i−1)+a_(i−1)·c_(i−1)+c_(i−1)·b_(i−1) and store c_(i) in R_(n) of the 1T1R array D₂; (S2-6) reading s_(i)* from R_(ib) of the 1T1R array D₁; inputting logic signals V_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0, V_(BL0˜(i−1))=0, V_(BLi)=s_(i)*, V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0, V_(SLi)=s_(i)* and V_(SL(i+1)˜(n−1))=0 to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i) and store s_(i) in R_(i) of the 1T1R array D₃; (S2-7) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S2-5); otherwise, proceeding to step (S2-8); (S2-8) inputting logic signals V_(WLn)=1, V_(BLn)=a_(n−2) and V_(SLn)=b_(n−2) to calculate c_(n−1)=a_(n−2)·b_(n−2)+a_(n−2)·c_(n−2)+c_(n−2)·b_(n−2) and store c_(n−1) in R_(n) of the 1T1R array D₂; (S2-9) reading s_(n−1)* from R_((n−1)b) of the 1T1R array D₁; inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−2))=0, V_(BL(n−1))=s_(n−1)*, V_(SL0˜(n−2))=0 and V_(SL(n−1))=s_(n−1)* to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array D₃; and (S2-10) inputting logic signals V_(WLn)=1, V_(BLn)=a_(n−1) and V_(SLn)=b_(n−1) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(n) of the 1T1R array D₂.
 11. An operation circuit based on the computing array according to claim 4 for implementing an optimized multi-bit step-by-step carry adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(0˜n−1) and carry information c₀, and n represents the number of bits of the operation data, comprising: a 1T1R array E₁, a 1T1R array E₂ and a 1T1R array E₃; the 1T1R array E₁ includes n 1T1R devices R_(0b)˜R_((n−1)b) for calculating and storing data s_(0˜n−1)*, word line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(WL0b)˜V_(WL(n−1)b), bit line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(BL0b)˜V_(BL(n−1)b), and source line control signals corresponding to R_(0b)˜R_((n−1)b) are respectively V_(SL0b)˜V_(SL(n−1)b); the 1T1R array E₁ is used for data backup; the 1T1R array E₂ includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculating and storing carry data c_(i), i is an integer from 0 to n, word line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(WL0c)˜V_(WLnc), bit line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), and source line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array E₃ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the intermediate data s_(0˜n−1)* calculated by the 1T1R array E₁ and the carry information c_(i) calculated by the 1T1R array E₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array E₃ through the data transmission circuit.
 12. An operating method based on the operation circuit according to claim 11, comprising: (S3-1) inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to write the input operational data a_(0˜n−1) into R_(0˜n−1) of the 1T1R array E₃; inputting logic signals V_(WL0b˜(n−1)b)=1, V_(BL0b˜(n−1)b)=a_(0˜n−1) and V_(SL0b˜(n−1)b)=a_(0˜n−1) to write the input operational data a_(0˜n−1) into R_(0b˜(n−1)b) of the 1T1R array E₁; inputting logic signals V_(WL0c˜nc)=1, V_(SL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to write the carry information c₀ into R_(0c˜nc) of the 1T1R array E₂; (S3-2) inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to calculate intermediate results and store s_(0˜n−1)* in R_(0˜n−1) of the 1T1R array E₃; inputting logic signals V_(WL0b˜(n−1)b)=b_(0˜n−1), V_(BL0b˜(n−1)b)=a_(0˜n−1) and V_(SL0b˜(n−1)b)=a_(0˜n−1) to calculate intermediate results s_(0˜n−1)* and store s_(0˜n−1)* in R_(0b˜(n−1)b) of the 1T1R array E₁; inputting logic signals V_(WL0)=0, V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array E₂; (S3-3) reading s₀* from R_(0b) of the 1T1R array E₁, and reading s₁* from R_(1b) of the 1T1R array E1; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜(n−1))=0, V_(BL0)=s₀*, V_(BL1)=s₁*, V_(BL2˜(n−1))=0, V_(SL0)=s₀* , V_(SL1)=s₁* and V_(SL2˜(n−1))=0 to calculate s₀=a₀⊕b₀⊕c₀ and s₁=a₁⊕b₁⊕c₁, and store s₀ in R₀ of the 1T1R array E₃ and s₁ in R₁ of the 1T1R array E₃; inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜nc)=1, V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜nc) of the 1T1R array E₂; (S3-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2; (S3-5) reading s_(i)* from R_(ib) of the 1T1R array E₁; inputting logic signals V_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0, V_(BL0˜(i−1))=0, V_(BLi)=s₁*, V_(BL(i+1)˜(n−1))=0, V_(SL0˜(i−1))=0, V_(SLi)=s_(i)* and V_(SL(i+1)˜(n−1))=0 to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i), and store s_(i) in R_(i) of the 1T1R array E₃; inputting logic signals V_(WL0c˜ic)=0, V_(WL(i+1)c˜nc)=1, V_(BL0c˜nc)=a_(i) and V_(SL0c˜nc)=b_(i) to calculate c_(i+1)=a_(i)⊕b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) in R_((i+1)c˜nc) of the 1T1R array E₂; (S3-6) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S3-5); otherwise, proceeding to a step (S3-7); and (3-7) reading s_(n−1)* from R_((n−1)b) of the 1T1R array E₁; inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−2))=0, V_(BL(n−1))=s_(n−1)*, V_(SL0˜(n−2))=0 and V_(SL(n−1))=s_(n−1)* to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array E₃; and inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1, V_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(nc) of the 1T1R array E₂.
 13. An operation circuit based on the computing array according to claim 4 for implementing a 2-bit data selector, in which a logic signal a, a logic signal b and a control signal Sel are input to output the logic signal a or the logic signal b by controlling a value of the control signal Sel, comprising: a 1T1R array F, wherein the 1T1R array F includes one 1T1R device R, a word line signal corresponding to R is V_(WL), a bit line signal corresponding to R is V_(BL), and a source line signal corresponding to R is V_(SL).
 14. An operating method based on the operation circuit according to claim 13, comprising: (S4-1) inputting logic signals V_(WL)=1, V_(BL)=a and V_(SL)=ā to initialize the 1T1R device R, and write the input logic signal a into R of the 1T1R array F; and (S4-2) inputting logic signals V_(WL)=Sel, V_(BL)=b and V_(SL)=b to input the logic signal b and the control signal Sel so as to select an output logic signal out, wherein the logic signal a and the logic signal b represent only two independent logic signals; when the control signal Sel=0, the output signal out=a; and when the control signal Sel=1, the output signal out=b.
 15. An operation circuit based on the computing array according to claim 4 for implementing a multi-bit carry select adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(0˜n−1) and carry information c₀, n represents the number of bits of the operation data, and in the calculation process, according to the carry information of each bit, an XNOR operation result or an XOR operation result of the corresponding bit of the operation data is selected as bit information of the sum, comprising: a 1T1R array G₁, a 1T1R array G₂ and a 1T1R array G₃; the 1T1R array G₁ includes n 1T1R devices R_(0x)˜R_((n−1)x) for calculating and storing XNOR operation results of data a_(0˜n−1) and b_(0˜n−1) (X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1)), word line control signals corresponding to R_(0x)˜R_((n−1)x) are respectively V_(WL0x)˜V_(WL(n−1)x), bit line control signals corresponding to R_(0x)˜R_((n−1)x) are respectively V_(BL0x)˜V_(BL(n−1)x), and source line control signals corresponding to R_(0x)˜R_((n−1)x) are respectively V_(SL0x)˜V_(SL(n−1)x); the 1T1R array G₂ includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculating carry data c_(i), i is an integer from 0 to n, word line control signals corresponding to R_(0c)˜R_(n), are respectively V_(WL0c)˜V_(WLnc), bit line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(BL0C)˜V_(BLnc), and source line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array G₃ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the XNOR operation results X_(0˜n−1) calculated by the 1T1R array G₁ and the carry information c_(i) calculated by the 1T1R array G₂ are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array G₃ through the data transmission circuit.
 16. An operating method based on the operation circuit according to claim 15, comprising: (S5-1) inputting logic signals V_(WL0x˜(n−1)x)=1, V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜(n−1)x)=b_(0˜n−1) to store the result b_(0˜n−1) of inverting the input operation data b_(0˜n−1) in R_(0x˜(n−1)x) of the 1T1R array G1; inputting logic signals V_(WL0c˜nc)=1, V_(SL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to store c₀ in R_(0c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to store the input operational data a_(0˜n−1) in R_(0˜n−1) of the 1T1R array G₃; (S5-2) inputting logic signals V_(WL0x˜(n−1)x)=a_(0˜n−1), V_(BL0x˜(n−1)x)=b_(0˜n−1) and V_(SL0x˜(n−1)x)=b_(0˜n−1) to calculate XNOR operation results X_(0˜n−1)=a_(0˜n−1) XNOR b_(0˜n−1) of the calculated data a_(0˜n−1) and b_(0˜n−1) and store X_(0˜n−1) in R_(0x˜(n−1)x) of the 1T1R array G₁; inputting logic signals V_(WL0c)=0, V_(WL1c-nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(n−1))=b_(0˜n−1), V_(BL0˜(n−1))=a_(0˜n−1) and V_(SL0˜(n−1))=a_(0˜n−1) to calculate XOR operation results s_(0˜n−1)*=a_(0˜n−1)⊕b_(0˜n−1) and store s_(0˜n−1)* in R_(0˜n−1) of the 1T1R array G₃; (S5-3) inputting logic signals V_(WL0c˜1c)=0, V_(WL2c˜nc)=1, V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜ne) of the 1T1R array G₂; inputting logic signals V_(WL0)=c₀, V_(WL1)=c₁, V_(WL2˜(n−1))=0, V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s₀ and s₁, and store s₀ in R₀ of the 1T1R array G₃ and s₁ in R₁ of the 1T1R array G₃; when c₀=0, s₀=a₀⊕b₀, and when c₁=0, s₀=a₀⊕b₀ ; when c₁=0, s₁=a₁⊕b₁, and when c₁=1, s₁=a₁⊕b₁ ; (S5-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2; (S5-5) inputting logic signals V_(WL0c˜ic)=0, V_(WL(i+1)c˜nc)=1, V_(BL0c˜nc)=a_(i) and V_(SL0c˜nc)=b_(i) to calculate c_(i+i)=a_(i)·b_(i)+a_(i)·c_(i)+c_(i)·b_(i) and store c_(i+1) in R_((i+1)c˜nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(i−1))=0, V_(WLi)=c_(i), V_(WL(i+1)˜(n−1))=0, V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s_(i) and store s_(i) in R_(i) of the 1T1R array G₃; when c_(i)=0, s_(i)=a_(i)⊕b_(i), and when c_(i)=1, s_(i)=a_(i) b_(i) ; (S5-6) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S5-5); otherwise, proceeding to a step (S5-7); and (S5-7) inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1, V_(SL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(nc) of the 1T1R array G₂; inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=c_(n−1), V_(BL0˜(n−1))=X_(0˜n−1) and V_(SL0˜(n−1))=X_(0˜n−1) to calculate s_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array G₃; when c_(n−1)=0, s_(n−1)=a_(n−1)⊕b_(n−1), and when c_(n−1)=1, s₇=a_(n−1)⊕b_(n−1) .
 17. An operation circuit based on the computing array according to claim 4 for implementing a multi-bit pre-calculation adder, in which sums s_(0˜n−1) and carry information c_(n) are calculated according to input data a_(0˜n−1) and b_(0˜n−1) and carry information c₀, and n represents the number of bits of the operation data, comprising: a 1T1R array H₁ and a 1T1R array H₂; the 1T1R array H₁ includes (n+1) 1T1R devices R_(0c)˜R_(nc) for calculating carry data c_(i), i is an integer from 0 to n, word line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(WL0c)˜V_(WLnc), bit line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(BL0c)˜V_(BLnc), and source line control signals corresponding to R_(0c)˜R_(nc) are respectively V_(SL0c)˜V_(SLnc); the 1T1R array H₂ includes n 1T1R devices R₀˜R_(n−1) for calculating and storing addition operation results s_(0˜n−1), word line control signals corresponding to R₀˜R_(n−1) are respectively V_(WL0)˜V_(WL(n−1)), bit line control signals corresponding to R₀˜R_(n−1) are respectively V_(BL0)˜V_(BL(n−1)), and source line control signals corresponding to R₀˜R_(n−1) are respectively V_(SL0)˜V_(SL(n−1)); and the carry information c_(i) calculated by the 1T1R array H₁ is converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array H₂ through the data transmission circuit.
 18. An operating method based on the operation circuit according to claim 17, comprising: (S6-1) inputting logic signals V_(WL0c˜nc)=1, V_(BL0c˜nc)=c₀ and V_(SL0c˜nc)=c₀ to store c₀ in R_(0c˜nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=c₀ and V_(SL0˜(n−1))=c₀ to store the input carry information c₀ in R_(0˜n−1) of the 1T1R array H₂; (S6-2) inputting logic signals V_(WL0c)=0, V_(WL1c˜nc)=1, V_(BL0c˜nc)=a₀ and V_(SL0c˜nc)=b₀ to calculate c₁=a₀·b₀+a₀·c₀+c₀·b₀ and store c₁ in R_(1c˜nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0˜(n−1))=a₀, V_(SL0)=b₀ and V_(SL1˜(n−1))=b₀ to calculate s₀′=c₀·a₀+c₀ ·a₀·b₀ +c₀·a₀ ·b₀ and c₁=a₀·b₀+a₀·c₀+c₀·b₀, and store s₀′ in R₀ of the 1T1R array H₂ and c₁ in R_(1˜n−1) of the 1T1R array Hz; (S6-3) inputting logic signals V_(WL0c˜1c)=0, V_(WL2e˜nc)=1, V_(BL0c˜nc)=a₁ and V_(SL0c˜nc)=b₁ to calculate c₂=a₁·b₁+a₁·c₁+c₁·b₁ and store c₂ in R_(2c˜nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−1))=1, V_(BL0)=b₀, V_(BL1˜(n−1))=a₁, V_(SL0)=c₁, V_(SL1)=b₁ and V_(SL2˜(n−1))=b₁ to calculate s₀=a₀⊕b₀⊕c₀, s₁′=c₁·a₁+c₁ ·a₁·b₁ +c₁·a₁ ·b₁ and c₂=a₁·b₁+a₁·c₁+c₁·b₁, and store s₀ in R₀ of the 1T1R array H₂, s₁′ in R₁ of the 1T1R array H₂ and c₂ in R_(2˜(n−1)) of the 1T1R array H₂; (S6-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=1; (S6-5) inputting logic signals V_(WL0c˜(i+1))0, V_(WL(i+2)c˜nc)=1, V_(BL0c˜nc)=a₁₊₁ and V_(SL0c˜nc)=b_(i+1) to calculate c_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c_(i+1)·b_(i+1) and store c_(i+2) in R_((i+2)c−nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(i−1))=0, V_(WLi˜(n−1))=1, V_(BL0˜(i−1))=0, V_(BLi)=b_(i), V_(BL(i+1)˜(n−1))=a_(i+1), V_(SL0˜(i−1))=0, V_(SLi)=c_(i+1), V_(SL(i+1))=b_((i+1)) and V_(SL(i+2)˜(n−1))=b_(i+1) to calculate s_(i)=a_(i)⊕b_(i)⊕c_(i), s_(i+1)′=c_(i+1)·a_(i+1)+c_(i+1) ·a_(i+1)+b_(i+1) +c_(i+1)·a_(i+1) ·b_(i+1) and c_(i+2)=a_(i+1)·b_(i+1)+a_(i+1)·c_(i+1)+c_(i+1)·b_(i+1) and store s_(i) in R_(i) of the 1T1R array H₂, s_(i+1)* in R_(i+1) of the 1T1R array H₂ and c_(i+2) in R_((i+2)˜(n−1)) of the 1T1R array H₂; (S6-6) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S6-5); otherwise, proceeding to a step (S6-7); (S6-7) inputting logic signals V_(WL0c˜(n−1)c)=0, V_(WLnc)=1, V_(BL0c˜nc)=a_(n−1) and V_(SL0c˜nc)=b_(n−1) to calculate c_(n)=a_(n−1)·b_(n−1)+a_(n−1)·c_(n−1)+c_(n−1)·b_(n−1) and store c_(n) in R_(nc) of the 1T1R array H₁; inputting logic signals V_(WL0˜(n−3))=0, V_(WL(n−2)˜(n−1))=1, V_(BL0˜(n−3))=0, V_(BL(n−2))=b_(n−2), V_(BL(n−1))=a_(n−1), V_(SL0˜(n−3))=0, V_(SL(n−2))=c_(n−1) and V_(SL(n−1))=b_(n−1) to calculate s_(n−2)=a_(n−2)⊕b_(n−2)⊕c_(n−2) and s_(n−1)*=c_(n−1)·a_(n−1)+c_(n−1) ·a_(n−1)·b_(n−1) +c_(n−1)·a_(n−1) ·b_(n−1) , and store s_(n−2) in R_(n−2) of the 1T1R array H₂ and s_(n−1)* in R_(n−1) of the 1T1R array H₂; and (S6-8) inputting logic signals V_(WL0˜(n−2))=0, V_(WL(n−1))=1, V_(BL0˜(n−2))=0, V_(BLn(n−1))=b_(n−1), V_(SL0˜(n−2))=0 and V_(SL(n−1))=c_(n) to calculate s_(n−1)=a_(n−1)⊕b_(n−1)⊕c_(n−1) and store s_(n−1) in R_(n−1) of the 1T1R array H₂.
 19. The computing array based on 1T1R device according to claim 2, wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit; the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result; an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array; an input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to the bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array; an input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to the source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array; the word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array; an input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem; a first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array; an input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.
 20. The computing array based on 1T1R device according to claim 3, wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit; the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result; an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array; an input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to the bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array; an input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to the source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array; the word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array; an input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem; a first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1 T1R array in the compute array; an input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit. 